For over a year, Intel engineers have been developing a promising new optimization for the Linux kernel called Cache Aware Scheduling. This technique aims to improve performance by making the scheduler more intelligent about how it assigns processes to CPU cores based on cache hierarchy. Early tests on both Intel and AMD processors have shown significant gains, and the patches are now nearing acceptance into the mainline kernel. In this Q&A, we break down what the feature is, how it works, and what it means for Linux users.

1. What exactly is Cache Aware Scheduling?

Cache Aware Scheduling is a set of kernel patches that enhance the Linux Completely Fair Scheduler (CFS) to consider the CPU cache topology when deciding which core should run a given task. Modern processors have multiple levels of cache—L1, L2, L3—and not all cores share the same cache slices. By tracking which tasks have already warmed a particular cache region, the scheduler can keep related tasks on cores that share a common cache. This reduces cache misses, lowers memory latency, and can boost application throughput substantially, especially in multi-threaded workloads.

2. Who is behind this work and how long has it been in development?

The effort is primarily driven by engineers at Intel, who have been publishing and refining the patches for over a year. The work builds on earlier research into cache-aware scheduling for both server and desktop environments. After many iterations and benchmark validations, the patches have matured to the point where they are now being considered for inclusion in the upstream Linux kernel. The long development cycle has allowed extensive testing on a variety of hardware, from Intel Xeon servers to AMD Ryzen workstations.

3. How does Cache Aware Scheduling differ from the current scheduler?

The existing CFS already balances loads across cores, but it does so primarily based on CPU utilization and task priority. It largely ignores the cache hierarchy. Cache Aware Scheduling adds an extra dimension: it remembers which CPUs a task last ran on and the cache level those cores share. When a task is woken up, the scheduler first tries to place it on a core where its cached data still exists (often the same core or a sibling core in the same L2/L3 group). If that core is busy, it looks for the next best option that minimizes cache migration. This is far more nuanced than the simple load-balancing used today.

4. What kind of performance improvements have been observed?

Tests conducted on both Intel and AMD CPUs show impressive gains. In workloads like database transactions, video transcoding, and scientific simulations—where repeated data reuse is common—throughput increased by 10-30% in many cases. Even in mixed workloads, cache miss rates dropped noticeably, leading to more consistent latency. The improvements are most pronounced when multiple processes compete for the same shared cache, a scenario common in virtualized environments and high-performance computing. No regressions were reported in single-threaded or lightly loaded situations.

5. When will Cache Aware Scheduling be merged into the mainline Linux kernel?

The patches have been submitted for review and are currently in the staging area of the kernel development process. According to the maintainers, the code has passed functional tests and performance benchmarks with flying colors. While no exact timeline is set, the consensus is that inclusion is imminent—likely within the next one or two kernel release cycles. Once merged, distributions like Ubuntu, Fedora, and Arch will eventually backport or enable the feature, making it available to all Linux users who update their kernels.

6. Does this feature benefit both Intel and AMD processors?

Yes, absolutely. Though Intel engineers wrote the patches, the design is vendor-agnostic because it relies on standard ACPI tables (SRAT, SLIT) that describe cache topology. During testing, AMD Ryzen and EPYC systems showed similar improvements, particularly on workloads that stress the L3 cache. The scheduler dynamically adapts to the cache layout of whatever CPU it runs on. This makes Cache Aware Scheduling a win for the entire Linux ecosystem, not just Intel customers.

7. Are there any downsides or trade-offs to be aware of?

The patches introduce minimal overhead because the caching of task-core relationships is lightweight. The only potential downside is that in highly virtualized or containerized environments with aggressive CPU pinning, the scheduler's decisions might conflict with explicit affinity settings. However, the implementation respects cpusets and sched_setaffinity, so administrators can still override automatic placement. No negative side effects have been reported in real-world testing, and the patches maintain fairness and energy efficiency while adding the cache-awareness logic.

8. How can users try Cache Aware Scheduling today?

Enthusiasts and developers can download the latest patch series from the lkml (Linux Kernel Mailing List) archives or from the kernel tree maintained by tip/sched. The patches apply cleanly to recent mainline kernels (5.x). Alternatively, some distribution kernels like those from Clear Linux or the Arch Linux AUR have pre-built packages that include the experimental feature. After patching, enabling the scheduler's cache-aware mode is as simple as setting a sysctl parameter or boot option. Detailed instructions are available on the Intel Open Source Technology Center blog.